Integer multipliers with overflow detection

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Gok M., Schulte M. J., Arnold M. G.

IEEE TRANSACTIONS ON COMPUTERS, cilt.55, sa.8, ss.1062-1066, 2006 (SCI-Expanded) identifier identifier

  • Yayın Türü: Makale / Tam Makale
  • Cilt numarası: 55 Sayı: 8
  • Basım Tarihi: 2006
  • Doi Numarası: 10.1109/tc.2006.126
  • Dergi Adı: IEEE TRANSACTIONS ON COMPUTERS
  • Derginin Tarandığı İndeksler: Science Citation Index Expanded (SCI-EXPANDED), Scopus
  • Sayfa Sayıları: ss.1062-1066
  • Anahtar Kelimeler: computer arithmetic, high-speed arithmetic algorithms, combinational logic, overflow detection, multiplication
  • Çukurova Üniversitesi Adresli: Evet

Özet

This paper presents a general approach for designing array and tree integer multipliers with overflow detection. The overflow detection techniques are based on an analysis of the magnitudes of the input operands. The overflow detection circuits operate in parallel with a simplified multiplier to reduce the overall area and delay.