Integer multipliers with overflow detection


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Gok M., Schulte M. J., Arnold M. G.

IEEE TRANSACTIONS ON COMPUTERS, vol.55, no.8, pp.1062-1066, 2006 (SCI-Expanded) identifier identifier

  • Publication Type: Article / Article
  • Volume: 55 Issue: 8
  • Publication Date: 2006
  • Doi Number: 10.1109/tc.2006.126
  • Journal Name: IEEE TRANSACTIONS ON COMPUTERS
  • Journal Indexes: Science Citation Index Expanded (SCI-EXPANDED), Scopus
  • Page Numbers: pp.1062-1066
  • Keywords: computer arithmetic, high-speed arithmetic algorithms, combinational logic, overflow detection, multiplication
  • Çukurova University Affiliated: Yes

Abstract

This paper presents a general approach for designing array and tree integer multipliers with overflow detection. The overflow detection techniques are based on an analysis of the magnitudes of the input operands. The overflow detection circuits operate in parallel with a simplified multiplier to reduce the overall area and delay.