Large operands are used in modern cryptography, signal processing and multimedia applications. Multiplication is one of the most used operations in these applications. The multiplication of the large operands is performed by a large multiplier hardware to achieve high speed. These circuits can be designed by using embedded arithmetic blocks offered by the state of the art FPGAs. In this paper, sequential large multiplier designs that can be mapped on these platforms are presented. Three design algorithms are proposed which differ depending on the use of the FPGA resources. 64-bit to 2048-bit multiplier implementations for these algorithms are modeled and synthesized. Compared to a fully combinational 256-bit multiplier the proposed 256-bit multiplier uses 15 times less resources and has 1.94 times more delay.