This paper presents single and multiple precision sequential large multiplier designs for field-programmable gate arrays. Both designs use the Karatsuba Ofman method. They are pipelined and can generate a full size (double operand size) or a single size product. The syntheses results show that the sequential large Karatsuba Ofman multiplier (SLKOM) implementations have up to 2.23 times less delay compared with the standard sequential large multipliers implementations presented in previous research. The 2048-bit multiple precision sequential Karatsuba Ofman large multiplier (MPSLKOM) implementation can simultaneously execute eight 256-bit multiplications. The MPSLKOM implementations use roughly 1% more registers and up to 3% more LUTs than the SLKOM implementations.