Design and implementation of an FPGA-based parallel graphics renderer for displaying CSG surfaces and volumes


Cevik U.

COMPUTERS & ELECTRICAL ENGINEERING, vol.30, no.2, pp.97-117, 2004 (Journal Indexed in SCI) identifier identifier

  • Publication Type: Article / Article
  • Volume: 30 Issue: 2
  • Publication Date: 2004
  • Doi Number: 10.1016/j.compeleceng.2002.10.001
  • Title of Journal : COMPUTERS & ELECTRICAL ENGINEERING
  • Page Numbers: pp.97-117

Abstract

In this paper, the design and implementation of a high-speed "CSG renderer" for displaying convex and concave objects and its performance analysis are presented. The renderer comprises a binary tree-structured depth generator that produces the depth values of a plane at each pixel on the display window simultaneously, and pipelined pixel processors that processes the depth values, a corner bender, and a frame-buffer.