High-speed arithmetic units in modern processors are expected to support multiplication operations with integers, fractions, and floating-point numbers. This paper presents hardware designs that can perform three modes of multiplication: (1) A double-width multiplication that returns a 2n-bit product. (2) A single-width integer multiplication that returns the n least-significant product bits and an overflow signal. (3) A truncated-fractional multiplication that returns the n most-significant product bits. The presented multipliers achieve up to 50% reduced power dissipation in integer and truncated-fractional multiplication modes of operation. For 16-bit or greater operand sizes the enhanced-functionality multiplier (EFM) designs use less than 10% more hardware compared to the conventional multipliers. (C) 2008 Elsevier B.V. All rights reserved.